Official NUC CCMAS syllabus
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Start studying CPE 505 free →Finite state machine: definition, mealy and Moore models, state diagram, state table, transition table; sequential circuits design using flip-flops, asynchronous and synchronous circuit design; algorithm state machine; design examples and exercises; structured design: design constructs, design levels, geometry-based interchange formats, computer-aided electronic system design tools, schematic circuit capture, hardware description languages, design process (simulation, synthesis), structural design decomposition; introduction to VHDL: VHDL language abstractions, design hierarchies, VHDL component, lexical description, VHDL source file, data types, data objects, language statements, concurrent VHDL, sequential VHDL, advanced features of VHDL (library, package and sub- programmes); structural level modelling, register-transfer level modelling, FSM with data path level modelling, algorithmic level modelling; introduction of ASIC, types of ASIC, ASIC design process, standard cell ASIC synthesis, FPGA design paradigm, FPGA synthesis, FPGA/CPLD architectures; VHDL Design: top-down design flow, verification, simulation alternatives, simulation speed, formal verification, recommendations for verification, writing RTL VHDL code for synthesis, top-down design with FPGA; VHDL synthesis, optimisation and mapping, constraints, technology library, delay calculation, synthesis tool, synthesis
Source: the Nigerian Universities Commission (NUC) Core Curriculum and Minimum Academic Standards (CCMAS). StudyOps loads this syllabus automatically when you study CPE 505.