Official NUC CCMAS syllabus

TEE 401 — Digital System Design with VHDL

3 units · TEE department course · Nigerian universities

Study TEE 401 the smart way

Sage already knows this exact syllabus — ask it anything about Digital System Design with VHDL, generate practice questions in your exam's format, and get a cram sheet that works offline.

Start studying TEE 401 free →

What you'll be able to do (official learning outcomes)

describe finite state machine and its applications in designing digital circuits
build advanced digital logic circuits by applying various reduction techniques and schemes
operate, debug, simulate and analyse complex digital designs in modern VHDL software
analyse and synthesise digital circuits using commercially available VHDL software
create FPGA designs and implement state-of-the-art ASIC/FPGA design methodologies for computer-aided design of logic circuits;
demonstrate practical skills in designing, synthesising and simulating digital systems.

Course contents

Finite state machine: definition, Mealy and Moore models, state diagram, state table, transition table. Sequential circuits design using flip-flops; asynchronous, and synchronous circuit design. Algorithm State Machine. Design examples and exercises. Structured design: design constructs, design levels, geometry-based interchange formats, computer aided electronic system design tools, Sshematic circuit capture, hardware description languages, design process (simulation, synthesis), structural design decomposition. Introduction to VHDL: VHDL language abstractions, design hierarchies, VHDL component, lexical description, VHDL source file, data types, data objects, language statements, concurrent VHDL, sequential VHDL, advanced features of VHDL (library, package and subprograms). Structural level modelling, register-transfer level modelling, FSM with data path level modelling, algorithmic level modelling. Introduction of ASIC, types of ASIC, ASIC design process, standard cell ASIC synthesis, FPGA design paradigm, FPGA synthesis, FPGA/CPLD architectures. VHDL design: top-down design flow, verification, simulation alternatives, simulation speed, formal verification, recommendations for verification, writing RTL VHDL code for synthesis, top-down design with FPGA. VHDL synthesis, optimization and mapping, constraints, technology library, delay calculation, synthesis tool, synthesis dir

Source: the Nigerian Universities Commission (NUC) Core Curriculum and Minimum Academic Standards (CCMAS). StudyOps loads this syllabus automatically when you study TEE 401.

TEE 401 — Digital System Design with VHDL

What you'll be able to do (official learning outcomes)

Course contents

More TEE courses